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12-bit, 170/210 msps 3.3 v a/d converter ad9430 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2010 analog devices, inc. all rights reserved. features snr = 65 db @ f in = 70 mhz @ 210 msps enob of 10.6 @ f in = 70 mhz @ 210 msps (C0.5 dbfs) sfdr = 80 dbc @ f in = 70 mhz @ 210 msps (C0.5 dbfs) excellent linearity: dnl = 0.3 lsb (typical) inl = 0.5 lsb (typical) 2 output data options: demultiplexed 3.3 v cmos outputs each @ 105 msps interleaved or parallel data output option lvds at 210 msps 700 mhz full-power analog bandwidth on-chip reference and track-and-hold power dissipation = 1.3 w typical @ 210 msps 1.5 v input voltage range 3.3 v supply operation output data format option data sync input and data clock output provided clock duty cycle stabilizer general description the ad9430 is a 12-bit, monolithic, sampling analog-to-digital converter (adc) optimized for high performance, low power, and ease of use. the product operates up to a 210 msps conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. all necessary functions, including a track-and-hold (t/h) and reference, are included on the chip to provide a complete conversion solution. the adc requires a 3.3 v power supply and a differential encode clock for full performance operation. the digital outputs are ttl/cmos or lvds compatible and support either twos complement or offset binary format. separate output power supply pins support interfacing with 3.3 v cmos logic. two output buses support demultiplexed data up to 105 msps rates in cmos mode. a data sync input is supported for proper output data port alignment in cmos mode, and a data clock output is available for proper output data timing. in lvds mode, the chip provides data at the encode clock rate. fabricated on an advanced bicmos process, the ad9430 is available in a 100-lead, surface-mount plastic package (100 e-pad tqfp) specified over the industrial temperature range (C40c to +85c). functional block diagram track- and-hold scalable reference adc 12-bit pipeline core lvds outputs clock management sense vref agnd drgnd drvdd avdd data, overrange in lvds or 2-port cmos dco? s5 s4 s2 s1 clk+ ds+ vin+ ad9430 12 vin? ds? clk? dco+ select cmos or lvds cmos outputs 02607-001 figure 1. applications wireless and wired broadband communications cable reverse path communications test equipment radar and satellite subsystems power amplifier linearization product highlights 1. high performance. maintains 65 db snr @ 210 msps with a 65 mhz input. 2. low power. consumes only 1.3 w @ 210 msps. 3. ease of use. lvds output data and output clock signal allow interface to current fpga technology. the on-chip reference and sample-and-hold provide flexibility in system design. use of a single 3.3 v supply simplifies system power supply design. 4. out of range (or) feature. the or output bit indicates when the input signal is beyond the selected input range. 5. pin compatible with 10-bit ad9411 (lvds only). .
ad9430 rev. e | page 2 of 44 table of contents dc specifications ............................................................................. 4 ? ac specifications.............................................................................. 6 ? digital specifications........................................................................ 7 ? switching specifications .................................................................. 8 ? timing diagrams.............................................................................. 9 ? absolute maximum ratings.......................................................... 10 ? explanation of test levels ......................................................... 10 ? esd caution................................................................................ 10 ? pin configurations and function descriptions ......................... 11 ? equivalent circuits ......................................................................... 15 ? typical performance characteristics ........................................... 16 ? terminology .................................................................................... 23 ? application notes ........................................................................... 25 ? theory of operation .................................................................. 25 ? encode input............................................................................... 25 ? analog input ............................................................................... 26 ? ds inputs (ds+, dsC)................................................................ 26 ? cmos outputs ........................................................................... 26 ? lvds outputs............................................................................. 27 ? voltage reference ....................................................................... 27 ? noise power ratio testing (npr) ............................................ 27 ? evaluation board, cmos mode................................................... 28 ? power connector........................................................................ 28 ? analog inputs ............................................................................. 28 ? gain.............................................................................................. 28 ? encode..................................................................................... 28 ? voltage reference ....................................................................... 28 ? data format select ..................................................................... 28 ? i/p timing select........................................................................ 28 ? timing controls ......................................................................... 28 ? cmos data outputs.................................................................. 29 ? crystal oscillator........................................................................ 29 ? optional amplifier..................................................................... 29 ? troubleshooting.......................................................................... 30 ? evaluation board, lvds mode .................................................... 36 ? power connector........................................................................ 36 ? analog inputs ............................................................................. 36 ? gain.............................................................................................. 36 ? clock ............................................................................................ 36 ? voltage reference ....................................................................... 36 ? data format select ..................................................................... 36 ? data outputs............................................................................... 36 ? crystal oscillator........................................................................ 36 ? outline dimensions ....................................................................... 42 ? ordering guide .......................................................................... 42 ?
ad9430 rev. e | page 3 of 44 revision history 9/10rev. d to rev. e change to general description section.........................................1 change to operating temperature range parameter, table 5..10 change to figure 4 ..........................................................................11 change to figure 5 ..........................................................................13 added exposed pad notation to outline dimensions ..............42 8/05rev. c to rev. d change to i vref spec units ...............................................................4 changes to minimum enob specification...................................6 added footnote for pin 33 in lvds mode ...................................7 change to lvds output section ..................................................27 added new evaluation board, cmos mode section................32 updated outline dimensions........................................................42 11/04rev. b to rev. c changes to specifications ................................................................4 changes to figure 60 .................................................................... 31 changes to lvds pcb bom ....................................................... 35 changes to figure 68 (evaluation boardlvds mode) ......... 36 updated outline dimensions ...................................................... 40 7/03rev. a to rev. b changed order of figure 1 and figure 2 ...................................... 5 updated tpc 13 .............................................................................14 changes to lvds outputs section..........................................20 add new ad9430 evaluation board, lvds mode section ......................................................................................... 27 updated outline dimensions ........................................... 32 3/03rev. 0 to rev. a upgraded for ad9430-210 .............................................. universal changes to features ................................................................. 1 changes to product highlights ...................................... 1 changes to specifications ..................................................... 2 changes to figure 2 ........................................................................ 5 changes to ordering guide .................................................. 6 change to pin function descriptions .......................... 7 edits to output propagation delay section. .............................. 10 added tpcs 5C8, 10C12, 14, 16, 18, 20, 22, 27, 31C32, 34 ...... 12 changes to tpcs............................................. 17, 19, 26, 35C36, 38 added text to encode input section ................................... 18 added ds inputs section ..........................................................19 change to table i ..........................................................................19 changes to lvds outputs section.............................................. 20 changes to voltage reference section .........................................20 replaced figure 12......................................................................... 20 change to troubleshooting section .............................................22 updated outline dimensions.............................................27 5/02revision 0: initial version
ad9430 rev. e | page 4 of 44 dc specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.536 v, lvds output mode, unless otherwise noted. table 1 . ad9430-170 ad9430-210 parameter temp test level min typ max min typ max unit resolution 12 bits accuracy no missing codes full vi guaranteed guaranteed offset error 25c i C3 +3 C3 +3 mv gain error 25c i C5 +5 C5 +5 % fs differential nonlinearity (dnl) 25c i C1 0.3 +1 C1 0.3 +1 lsb full vi C1 0.3 +1.5 C1 0.3 +1.5 lsb integral nonlinearity (inl) 25c i C1.5 0.5 +1.5 C1.75 0.3 +1.75 lsb full vi C2.25 0.5 +2.25 C2.5 0.3 +2.5 lsb temperature drift offset error full v 58 58 v/c gain error full v 0.02 0.02 %/c reference out (vref) full v +0.12/C0.24 +0.12/C0.24 mv/c reference reference out (vref) 25c i 1.15 1.235 1.3 1.15 1.235 1.3 v output current 1 25c iv 3.0 3.0 ma i vref input current 2 25c i 20 20 a i sense input current 2 25c i 1.6 5.0 1.6 5.0 ma analog inputs (vin+, vinC) 3 differential input voltage range (s5 = gnd) full v 1.536 1.536 v differential input voltage range (s5 = avdd) full v 0.766 0.766 v input common-mode voltage full vi 2.65 2.8 2.9 2.65 2.8 2.9 v input resistance full vi 2.2 3 3.8 2.2 3 3.8 k input capacitance 25c v 5 5 pf power supply (lvds mode) avdd full iv 3.1 3.3 3.6 3.2 3.3 3.6 v drvdd full iv 3.0 3.3 3.6 3.0 3.3 3.6 v supply currents i analog (avdd = 3.3 v) 4 full vi 335 372 390 450 ma i digital (drvdd = 3.3 v) 4 full vi 55 62 55 62 ma power dissipation 4 full vi 1.29 1.43 1.5 1.7 w power supply rejection 25c v C7.5 C7.5 mv/v
ad9430 rev. e | page 5 of 44 ad9430-170 ad9430-210 parameter temp test level min typ max min typ max unit power supply (cmos mode) avdd full iv 3.1 3.3 3.6 3.2 3.3 3.6 v drvdd full iv 3.0 3.3 3.6 3.0 3.3 3.6 v supply currents i avdd (avdd = 3.3 v) 5 full iv 335 372 390 450 ma i drvdd (drvdd = 3.3 v) 5 full iv 24 30 30 30 ma power dissipation 5 full iv 1.1 1.3 w power supply rejection 25c v C7.5 C7.5 mv/v 1 internal reference mode; sense = floats. 2 external reference mode; sense = drvdd, vref driven by external 1.23 v reference. 3 s5 (pin 1) = gnd. see the section. s5 = gnd in all dc and ac tests, unless otherwise noted. analog input 4 i avdd and i drvdd are measured with an analog input of 10.3 mhz, C0.5 dbfs, sine wave, rated encode rate, and in lvds output mode. see typical pe rformance characteristics and applicat ion notes sect ions for i drvdd . power consumption is measured with a dc input at rated encode rate in lvds output mode. 5 i avdd and i drvdd are measured with an analog input of 10.3 mhz, C0.5 dbfs, sine wave, rated encode rate, and in cmos output mode. see typical p erformance characteristics and applicat ion notes sect ions for i drvdd . power consumption is measured with a dc input at rated encode rate in cmos output mode.
ad9430 rev. e | page 6 of 44 ac specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.536 v, lvds output mode, unless otherwise noted. 1 table 2. ad9430-170 ad9430-210 parameter temp test level min typ max min typ max unit snr analog input @ C0.5 dbfs 10 mhz 25c i 63.5 65 62.5 64.5 db 70 mhz 25c i 63 65 62.5 64.5 db 100 mhz 25c v 65 64.5 db 240 mhz 25c v 61 61 db sinad analog input @ C0.5 dbfs 10 mhz 25c i 63.5 65 62.5 64.5 db 70 mhz 25c i 63 65 62.5 64.5 db 100 mhz 25c v 65 64.5 db 240 mhz 25c v 60 60 db effective number of bits (enob) 10 mhz 25c i 10.3 10.6 10.2 10.5 bits 70 mhz 25c i 10.3 10.6 10.2 10.5 bits 100 mhz 25c v 10.6 10.5 bits 240 mhz 25c v 9.8 9.8 bits worst harmonic (2nd or 3rd) analog input @ C0.5 dbfs, 10 mhz 10 mhz 25c i C85 C75 C84 C74 dbc 70 mhz 25c i C85 C75 C84 C74 dbc 100 mhz 25c v C77 C77 dbc 240 mhz 25c v C63 C63 dbc worst harmonic (4th or higher) analog input @ C0.5 dbfs, 10 mhz 10 mhz 25c i C87 C78 C87 C77 dbc 70 mhz 25c i C87 C78 C87 C77 dbc 100 mhz 25c v C77 C77 dbc 240 mhz 25c v C63 C63 dbc two-tone imd d 2 f1, f2 @ ?7 dbfs 25c v C75 C75 dbc analog input bandwidth 25c v 700 700 mhz 1 all ac specifications tested by differentially driving clk+ and clk?. 2 f1 = 28.3 mhz, f2 = 29.3 mhz.
ad9430 rev. e | page 7 of 44 digital specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, unless otherwise noted. table 3. test ad9430-170 ad9430-210 parameter temp level min typ max min typ max unit encode and ds inputs (clk+, clkC, ds+, dsC) 1 differential input voltage 2 full iv 0.2 0.2 v common-mode voltage 3 full vi 1.375 1.5 1.575 1.375 1.5 1.575 v input resistance full vi 3.2 5.5 6.5 3.2 5.5 6.5 k input capacitance 25c v 4 4 pf logic inputs (s1, s2, s4, s5) logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v logic 1 input current full vi 190 190 a logic 0 input current full vi 10 10 a input resistance 25c v 30 30 k input capacitance 25c v 4 4 pf logic outputs (cmos mode) logic 1 voltage 4 full iv drvdd drvdd v C0.05 C0.05 logic 0 voltage 4 full iv 0.05 0.05 v logic outputs (lvds mode) 4 , 5 v od differential output voltage full vi 247 454 247 454 mv v os output offset voltage full vi 1.125 1.375 1.125 1.375 v output coding twos complement or binary twos complement or binary 1 encode (clock) and ds inputs identical on the chip. see the section. equivalent circuits 2 all ac specifications tested by driving clk+ and clkC differentially, |(clk+) C (clkC)| > 200 mv. 3 encode (clock) inputs common-mode can be externally set, such that 0.9 v < (clk+ or clk?) < 2.6 v. 4 digital output logic levels: drvdd = 3.3 v, c load = 5 pf. 5 lvds r term = 100 , lvds output current set resistor (r set ) = 3.74 k (1% tolerance).
ad9430 rev. e | page 8 of 44 switching specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, unless otherwise noted. table 4. test ad9430-170 ad9430-210 parameter (conditions) temp level min typ max min typ max unit maximum conversion rate 1 full vi 170 210 msps minimum conversion rate 1 full v 40 40 msps clk+ pulse width high (t eh ) 1 full iv 2 12.5 2 12.5 ns clk+ pulse width low (t el ) 1 full iv 2 12.5 2 12.5 ns ds input setup time (t sds ) 2 full iv C0.5 C0.5 ns ds input hold time (t hds ) 2 full iv 1.75 1.75 ns output (cmos mode) valid time (t v ) full iv 2 2 ns propagation delay (t pd ) full iv 3.8 5 3.8 5 ns rise time (t r ) (20% to 80%) 25c v 1 1 ns fall time (t f ) (20% to 80%) 25c v 1 1 ns dco propagation delay (t cpd ) full iv 3.8 5 3.8 5 ns data to dco skew (t pd to t cpd ) full iv C0.5 0 +0.5 C0.5 0 +0.5 ns interleaved mode (a, b latency) full iv 14, 14 14, 14 cycles parallel mode (a, b latency) full iv 15, 14 15, 14 cycles output (lvds mode) valid time (t v ) full vi 2.0 2.0 ns propagation delay (t pd ) full vi 3.2 4.3 3.2 4.3 ns rise time (t r ) (20% to 80%) 25c v 0.5 0.5 ns fall time (t f ) (20% to 80%) 25c v 0.5 0.5 ns dco propagation delay (t cpd ) full vi 1.8 2.7 3.8 1.8 2.7 3.8 ns data to dco skew (t pd C t cpd ) full iv 0.2 0.5 0.8 0.2 0.5 0.8 ns latency full iv 14 14 cycles aperture delay (t a ) 25c v 1.2 1.2 ns aperture uncertainty (jitter, t j ) 25c v 0.25 0.25 ps rms out of range recovery time (cmos and lvds) 25c v 1 1 cycles 1 all ac specifications tested by differentially driving clk+ and clk?. 2 ds inputs used in cmos mode only.
ad9430 rev. e | page 9 of 44 timing diagrams port a da11?da0 port b db11?db0 parallel data out port a da11?da0 port b db11?db0 clk+ clk? ds+ ds? interleaved data out static static static static static invalid invalid invalid invalid invalid invalid invalid t sds 14 cycles t pd t v n n+2 n+3 n+1 n n+2 n+1 n+3 t cpd t hds dco+ dco? 02607-002 figure 2. cmos timing diagram n?14 n?13 n n+1 a in clk+ clk? data out dco+ dco? n n+1 n ? 1 t eh t el 1/f s t pd 14 cycles t cpd 02607-003 figure 3. lvds timing diagram
ad9430 rev. e | page 10 of 44 absolute maximum ratings table 5. parameter rating avdd, drvdd 4 v analog inputs ?0.5 v to avdd + 0.5 v digital inputs ?0.5 v to drvdd + 0.5 v refin inputs C0.5 v to avdd + 0.5 v digital output current 20 ma operating temperature range ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c maximum case temperature 150c ja 1 25c/w, 32c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels table 6. level description i 100% production tested. ii 100% production tested at 25c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. 1 typical ja = 32c/w (heat slug not soldered); typical ja = 25c/w (heat slug soldered) for multilayer board in still air with solid ground plane. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefor e, proper esd precautions are re commended to avoid performance degradation or loss of functionality.
ad9430 rev. e | page 11 of 44 pin configurations and function descriptions pin 1 ad9430 cmos pinout top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 76 77 7879 80 81 82 83 84 8586 87 8889 90 91 92 93 94 95 96 97 98 99 100 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 02607-004 agnd avdd avdd avdd agnd agnd ds+ ds? avdd agnd clk+ clk? agnd avdd avdd agnd dnc dnc db0 db1 db2 drvdd drgnd db3 db4 drvdd drgnd da4 da3 da2 da1 da0 dnc drgnd dnc dnc dco+ dco? drvdd drgnd or_b db11 db10 db9 db8 db7 drvdd drgnd db6 db5 da9 da8 da7 da6 da5 agnd avdd avdd agnd agnd avdd avdd agnd agnd agnd avdd avdd avdd agnd agnd or_a da11 drvdd drgnd da10 s5 dnc s4 agnd s2 s1 dnc avdd agnd s ense vref agnd agnd avdd avdd agnd agnd avdd avdd agnd vin+ vin? agnd avdd agnd notes 1. the ad9430 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. figure 4. cmos dual-mode pin configuration table 7. cmos mode pin function descriptions pin number mnemonic description 1 s5 full-scale adjust pin. avdd sets f s = 0.768 v p-p differential, gnd sets f s = 1.536 v p-p differential. 2, 7, 42, 43, 65, 66, 68 dnc do not connect. 3 s4 interleaved, parallel select pin. high = interleaved. 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 agnd 1 analog ground. 5 s2 output mode select. low = dual-port cmos, high = lvds. 6 s1 data format select. low = binary, high = twos complement for both cmos and lvds modes. 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 avdd 3.3 v analog supply. 10 sense reference mode select pin. float for internal reference operation. 11 vref 1.235 v reference i/ofunction dependent on sense. 21 vin+ analog inputtrue. 22 vinC analog inputcomplement. 32 ds+ data sync (input)true. tie low if not used. 33 dsC 2 data sync (input)complement. tie high if not used.
ad9430 rev. e | page 12 of 44 pin number mnemonic description 36 clk+ clock inputtrue. 37 clkC clock inputcomplement. 44 db0 b port output data bit (lsb). 45 db1 b port output data bit. 46 db2 b port output data bit. 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 48, 53, 61, 67, 74, 82 drgnd 1 digital output ground. 49 db3 b port output data bit. 50 db4 b port output data bit. 51 db5 b port output data bit. 52 db6 b port output data bit. 55 db7 b port output data bit. 56 db8 b port output data bit. 57 db9 b port output data bit. 58 db10 b port output data bit. 59 db11 b port output data bit (msb). 60 or_b b port overrange. 63 dcoC data clock outputcomplement. 64 dco+ data clock outputtrue. 69 da0 a port output data bit (lsb). 70 da1 a port output data bit. 71 da2 a port output data bit. 72 da3 a port output data bit. 73 da4 a port output data bit. 76 da5 a port output data bit. 77 da6 a port output data bit. 78 da7 a port output data bit. 79 da8 a port output data bit. 80 da9 a port output data bit. 81 da10 a port output data bit. 84 da11 a port output data bit (msb). 85 or_a a port overrange. 1 agnd and drgnd should be tied to gether to a common ground plane. 2 ds complement (ds?); can be tied to avdd (as recommended) or left floating with no ill effects.
ad9430 rev. e | page 13 of 44 pin 1 ad9430 lvds pinout top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 76 77 78 79 80 81 82 83 84 8586 87 8889 90 91 92 93 94 95 96 97 98 99 100 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 02607-005 s5 dnc s4 agnd s2 s1 lvdsbias avdd agnd sense vref agnd agnd avdd avdd agnd agnd avdd avdd agnd vin+ vin? agnd avdd agnd notes 1. the ad9430 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. agnd avdd avdd avdd agnd agnd gnd avdd avdd agnd clk+ clk? agnd avdd avdd agnd dnc dnc dnc dnc dnc drvdd drgnd d0? d0+ drvdd drgnd d8+ d8? d7+ d7? d6+ d6? drgnd d5+ d5? dco+ dco? drvdd drgnd d4+ d4? d3+ d3? d2+ d2e drvdd drgnd d1+ d1? d11? d10+ d10? d9+ d9? agnd avdd avdd agnd agnd avdd avdd agnd agnd agnd avdd avdd avdd agnd agnd or+ or? drvdd drgnd d11+ figure 5. lvds mode pin configuration table 8. lvds mode pin function descriptions pin uber mneonic description 1 s5 full-scale adjust pin. avdd sets f s = 0.768 v p-p differential, gnd sets f s = 1.536 v p-p differential. 2, 42 to 46 dnc do not connect. 3 s4 control pin for cmos mode. tie low when operating in lvds mode. 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 agnd 1 analog ground. 5 s2 output mode select. gnd = dual-port cmos; avdd = lvds. 6 s1 data format select. gnd = binary, avdd = twos complement. 7 lvdsbias set pin for lvds output current. place 3.74 kw resistor terminated to ground. 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95, avdd 2 3.3 v analog supply. 98, 99 10 sense reference mode select pin. float for internal reference operation. 11 vref 1.235 v reference i/ofunction dependent on sense. 21 vin+ analog inputtrue.
ad9430 rev. e | page 14 of 44 pin number mnemonic description 22 vinC analog inputcomplement. 32 gnd data sync (input)not used in lvds mode. tie to gnd. 36 clk+ clock inputtrue (lvpecl levels). 37 clkC clock inputcomplement (lvpecl levels). 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 48, 53, 61, 67, 74, 82 drgnd 1 digital output ground. 49 d0C d0 complement output bit (lsb). 50 d0+ d0 true output bit (lsb). 51 d1C d1 complement output bit. 52 d1+ d1 true output bit. 55 d2C d2 complement output bit. 56 d2+ d2 true output bit. 57 d3C d3 complement output bit. 58 d3+ d3 true output bit. 59 d4C d4 complement output bit. 60 d4+ d4 true output bit. 63 dcoC data clock outputcomplement. 64 dco+ data clock outputtrue. 65 d5C d5 complement output bit. 66 d5+ d5 true output bit. 68 d6C d6 complement output bit. 69 d6+ d6 true output bit. 70 d7C d7 complement output bit. 71 d7+ d7 true output bit. 72 d8C d8 complement output bit. 73 d8+ d8 true output bit. 76 d9C d9 complement output bit. 77 d9+ d9 true output bit. 78 d10C d10 complement output bit. 79 d10+ d10 true output bit. 80 d11C d11 complement output bit. 81 d11+ d11 true output bit. 84 orC overrange complement output bit. 85 or+ overrange true output bit. 1 agnd and drgnd should be tied to gether to a common ground plane. 2 pin 33 can be tied to avdd (as recommended) or left floating with no ill effects
ad9430 rev. e | page 15 of 44 equivalent circuits clk+ or ds+ 12k 10k 150 150 12k 10k avdd clk? or ds? 02607-080 figure 6. encode and ds input vin+ 3.5k 20k 3.5k 20k av d d vin? 02607-007 figure 7. analog inputs s1, s2, s4, s5 vdd 30k 02607-008 figure 8. s1 to s5 inputs a1 vref 1k sense 200 0.1 f disable a1 vdd k full scale s5 = 0 ?> k = 1.24 s5 = 1 ?> k = 0.62 ? + 1v 02607-009 figure 9. vref, sense i/o dx dr v dd 02607-010 figure 10. data outputs (cmos mode) drvdd dx? dx+ v v v v 02607-011 figure 11. data outputs (lvds mode)
ad9430 rev. e | page 16 of 44 8 5 typical performance characteristics charts at 170 msps, 210 msps for C170, C210 grades, respectively. avdd, drvdd = 3.3 v, t = 25c, a in differential drive, full scale = 1.536 v, internal reference unless otherwise noted. mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?10 ?20 ?80 ?30 ?40 ?50 ?60 ?70 ?90 snr = 65.2db sinad = 65.1db h2 = ?88.8dbc h3 = ?88.1dbc sfdr = 87dbc 02607-012 figure 12. fft: f s = 170 msps, a in = 10.3 mhz @ ?0.5 dbfs, lvds mode mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?10 ?20 ?80 ?30 ?40 ?50 ?60 ?70 ?90 8 5 snr = 65.1db sinad = 64.9db fund = ?0.50dbfs h2 = ?88.6dbc h3 = ?94.6dbc sfdr = 85.9dbc 02607-013 figure 13. fft: f s = 170 msps, a in = 65 mhz @ C0.5 dbfs, lvds mode mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?10 ?20 ?80 ?30 ?40 ?50 ?60 ?70 ?90 8 5 snr = 64.93db sinad = 64.85db fund = ?0.44dbfs h2 = ?92.1dbc h3 = ?90.1dbc sfdr = 75.6dbc 02607-015 figure 14. fft: f s = 170 msps, a in = 65 mhz @ C0.5 dbfs, cmos mode mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?10 ?20 ?80 ?30 ?40 ?50 ?60 ?70 ?90 8 5 snr = 62.99dbfs sinad = 61.45dbfs h2 = ?66.8dbc h3 = ?82.5dbc sfdr = 66.1dbc 02607-015 figure 15. fft: f s = 170 msps, a in = 10.3 mhz @ C0.5 dbfs, single-ended input, full scale = 0.76 v, lvds mode db 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 1530 45 60 7590105 snr = 63.6db sinad = 62.9db h2 = ?82.5dbc h3 = ?78.6dbc sfdr = 77.7dbc mhz 02607-016 figure 16. fft: f s = 210 msps, a in = 10.3 mhz @ C0.5 dbfs, lvds mode db 0 ?20 ?10 ?30 ?40 ?60 ?70 ?50 ?80 ?90 ?100 0 15 30 45 60 75 90 105 snr = 63.1db sinad = 62.8db h2 = ?81.1dbc h3 = ?76dbc sfdr = ?76dbc mhz 02607-017 figure 17. fft: f s = 210 msps, a in = 65 mhz @ C0.5 dbfs, cmos mode
ad9430 rev. e | page 17 of 44 db 0 ?10 ?20 ?30 ?40 ?60 ?70 ?80 ?90 ?50 ?100 0 15 30 45 60 75 90 105 mhz snr = 63.5db sinad = 62.6db h2 = ?79dbc h3 = ?76.1dbc sfdr = 75.2dbc 02607-018 figure 18. fft: f s = 210 msps, a in = 65 mhz @ C0.5 dbfs, lvds mode a in (mhz) db 85 80 75 70 65 60 55 50 45 40 0 100 150 250 350 50 200 300 400 sfdr snr sinad full scale = 1.5 02607-019 figure 19. snr, sinad, and sfdr vs. a in frequency, f s = 210 msps, a in @ C0.5 dbfs, lvds mode a in (mhz) 0 200 400 50 100 150 250 300 350 db 100 40 90 50 80 70 60 second third sfdr 02607-020 figure 20. harmonic distortion (2 nd and 3 rd ) and sfdr vs. a in frequency 0 153045607590105 db 0 ?60 ?90 ?40 ?20 ?70 ?30 ?10 ?50 mhz ?80 ?100 snr = 63.3db sinad = 63.1db h2 = ?80.38dbc h3 = ?81.8dbc sfdr = 80.8dbc 02607-021 figure 21. fft: f s = 213 msp, a in = 100 mhz @ C0.5 dbfs, lvds mode a in (mhz) db 85 80 75 70 65 60 55 50 45 40 0 100 150 250 350 50 200 300 400 sinad snr full scale = 0.75 02607-022 figure 22. snr and sinad vs. a in frequency, f s = 210 msps, a in @ C0.5 dbfs, lvds mode, full scale = 0.76 v a in (mhz) 0 200 400 50 100 150 250 300 350 db 100 40 90 50 80 70 60 second third sfdr 02607-023 figure 23. harmonic distortion (2 nd and 3 rd ) and sfdr vs. a in frequency, f s = 170 msps, cmos mode
ad9430 rev. e | page 18 of 44 a in (mhz) db 70 66 68 60 62 64 58 56 54 52 50 0 100 150 50 200 250 300 350 400 ?170 sinad ?210 sinad ?210 snr ?170 snr 02607-024 figure 24. snr and sinad vs. a in frequency, f s = 170 msps/210 msps, a in @ C0.5 dbfs, lvds mode a in (mhz) db 85 80 75 70 65 60 55 50 45 40 0 100 150 250 350 50 200 300 400 sinad snr sfdr 02607-025 figure 25. snr and sinad, sfdr vs. a in frequency, f s = 210 msps, a in @ C0.5 dbfs, cmos mode mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?10 ?20 ?80 ?30 ?40 ?50 ?60 ?70 ?90 8 5 sfdr = 75dbc 02607-026 figure 26. two-tone intermodulation distortion (28.3 mhz and 29.3 mhz, lvds mode, f s = 170 msps) db 0 ?30 ?60 ?90 ?120 0 102030405060 8090100 70 mhz sfdr = 63dbc 02607-027 figure 27. two-tone intermodulation distortion (59 mhz and 60 mhz), lvds mode, f s = 210 msps mhz 0 250 50 100 150 200 db 95 50 90 55 80 75 65 85 70 60 sinad sfdr 02607-028 figure 28. sinad and sfdr vs. clock rate (a in = 10.3 mhz @ C0.5 dbfs, lvds mode), C170 grade mhz db 85 80 75 70 65 60 55 50 45 40 0 100 150 250 50 200 sinad snr sfdr 02607-029 figure 29. snr and sinad, sfdr vs. clock rate (a in = 10.3 mhz, @ C0.5 dbfs), lvds mode, C210 grade
ad9430 rev. e | page 19 of 44 analog supply current cmos mode analog supply current lvds mode output supply current lvds mode output supply current cmos mode encode (msps) 100 220 140 160 180 200 120 i avdd (analog supply current) (ma) 400 0 350 50 250 150 300 200 100 i drvdd (output supply current) (ma) 80 60 40 20 0 02607-030 figure 30. i avdd and i drvdd vs. clock rate (a in = 10.3 mhz @ C0.5 dbfs) 170 msps grade, c load = 5 pf encode (msps) i avdd (analog supply current) (ma) i drvdd (output supply current) (ma) 450 400 350 300 250 200 150 100 50 0 90 80 70 60 50 40 30 20 10 0 100 140 160 200 220 240 120 180 analog supply current lvds mode output supply current lvds mode output supply current cmos mode analog supply current cmos mode 02607-031 figure 31. i avdd and i drvdd vs. clock rate (a in = 10.3 mhz @ C0.5 dbfs), 210 msps grade, c load = 5 pf sinad snr sfdr encode positive duty cycle (%) 10 60 90 20 40 50 70 80 30 db 85 50 80 75 70 65 60 55 02607-032 figure 32. sinad and sfdr vs. clock pulse width high (a in = 10.3 mhz @ C0.5 dbfs, 170 msps, lvds) encode positive duty cycle (%) db 80 75 70 65 60 55 50 20 40 50 70 30 60 80 sinad snr sfdr 02607-033 figure 33. snr, sinad, and sfdr vs. encode pulse width high, (a in = 10.3 mhz @ C0.5 dbfs, 210 msps, lvds) i load (ma) 08 147 2 v refout (v) 1.4 0 1.2 1.0 0.8 0.6 0.4 0.2 r o = 13 typ 02607-034 5 36 figure 34. v refout vs. i load temperature (c) ?50 10 95 ?30 ?10 30 50 70 90 gain error (%) ?2.0 1.5 ?1.0 1.0 0.5 0 ?0.5 ?1.5 % gain error using ext ref 2.0 02607-035 figure 35. full-scale gain error vs. temperature (a in = 10.3 mhz @ C0.5 dbfs, 170 msps/210 msps, lvds)
ad9430 rev. e | page 20 of 44 avdd (v) 2.5 3.1 2.7 2.9 3.3 3.5 3.7 3.9 v ref (v) 1.250 1.225 1.230 1.245 1.240 1.235 02607-036 figure 36. v ref output voltage vs. avdd temperature (c) ?50 10 ?30 ?10 30 50 70 90 db 95 60 90 70 85 80 75 65 third second sfdr snr sinad 02607-037 figure 37. snr, sinad, and sfdr vs. temperature (a in = 10.3 mhz @ C0.5 dbfs, 170 msps) temperature (c) db 65 64 63 62 61 60 59 58 57 56 55 ?45 ?5 15 55 ?25 35 75 avdd = 3.6 avdd = 3.3 avdd = 3.135 avdd = 3.0 02607-038 figure 38. sinad vs. temperature, avdd (a in = 70 mhz @ C0.5 db, 210 msps, lvds mode) code 0 4000 500 1500 2500 3000 1000 2000 3500 lsb 1.00 ?1.00 0.75 ?0.75 0.25 ?0.25 0.50 0 ?0.50 02607-039 figure 39. typical inl plot (a in = 10.3 mhz @ C0.5 dbfs, 170 msps, lvds) code 0 4000 500 1500 2500 3000 1000 2000 3500 lsb 1.00 ?1.00 0.75 ?0.75 0.25 ?0.25 0.50 0 ?0.50 02607-040 figure 40. typical dnl plot (a in = 10.3 mhz @ C0.5 dbfs) analog input level (dbfs) ?100 0 ?70 ?50 ?30 ?20 ?60 ?40 ?10 ?80 ?90 db 100 0 70 10 50 30 60 40 20 80 90 sfdr ?dbfs sfdr ?dbc 80db reference line 02607-041 figure 41. sfdr vs. a in input level , a in @ 10.3 mhz, 170 msps, lvds mode
ad9430 rev. e | page 21 of 44 db 90 80 70 60 50 40 30 20 10 0 ?90 ?70 ?60 ?40 ?20 ?80 ?50 ?30 ?10 0 sfdr dbc lvds mode full scale = 1.5 sfdr dbc cmos mode full scale = 1.5 80db reference line 02607-042 figure 42. sfdr vs. a in input level, a in @ 10.3 mhz, 210 msps, lvds/cmos modes db 90 80 70 60 50 40 30 20 10 0 ?90 ?70 ?60 ?40 ?20 ?80 ?50 ?30 ?10 0 sfdr dbc lvds mode full scale = 1.5 sfdr dbc lvds mode full scale = 0.75 80db reference line 02607-043 figure 43. sfdr vs. a in input level, a in @ 10.3 mhz, 210 msps, lvds mode, full scale = 0.76 v/1.536 v mhz 2.65 42.5 21.25 noise input level (db) 0 ?140 ?40 ?120 ?100 ?60 ?80 ?20 npr = 56.95db encode = 170msps notch @ 19mhz 02607-044 figure 44. noise power ratio plot mhz db 0 ?20 ?40 ?60 ?80 ?100 19.2 38.4 19.2 47.6 02607-045 figure 45. w-cdma four channels centered at 38.4 mhz, f s = 153.6 mhz, lvds mode full-scale range (v) 0 2.5 2.0 1.0 1.5 0.5 db 90 0 70 10 50 30 60 40 20 80 sinad snr sfdr 02607-046 figure 46. snr, sinad, and sfdr vs. full-scale range, s5 = 0, full-scale range varied by adjusting vref, 170 msps temperature (c) ?40 100 60 20 40 ?20 0 80 ns 4.5 2.5 4.0 3.5 3.0 tpd tcpd 02607-047 figure 47. propagation delay vs. temperature, lvds mode, 170 msps/210 msps
ad9430 rev. e | page 22 of 44 tcpd (clockout rising) temperature (c) ?40 100 60 20 40 ?20 0 80 ns 4.5 2.5 4.0 3.5 3.0 tpdf (data falling) tpdr (data rising) 02607-048 figure 48. propagation delay vs. temperature, cmos mode, 170 msps/210 msps rset (k ) 01 10 6 21 v dif (mv) 900 0 700 500 300 800 600 400 200 100 1.4 0.5 1.2 1.0 0.8 1.3 1.1 0.9 0.7 0.6 v os (v) v os v od 02607-049 8 4 4 2 figure 49. lvds output swing, common-mode voltage vs. rset, placed at lvdsbias, 170 msps/210 msps
ad9430 rev. e | page 23 of 44 terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. crosstalk coupling onto one channel being driven by a low level (C40 dbfs) signal when the adjacent interfering channel is driven by a full-scale signal. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. peak-to-peak differential is computed by rotating the input phase 180 and again taking the peak measurement. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) calculated from the measured snr based on the equation 6.02 db1.76 ? = measured snr enob encode pulse width/duty cycle pulse width high is the minimum amount of time the encode pulse (clock pulse) should be left in a logic 1 state to achieve rated performance; pulse width low is the minimum time the encode pulse should be left in a low state. see the timing implications of changing t eh in the encode input section. at a given clock rate, these specifications define an acceptable encode duty cycle. full-scale input power expressed in dbm. computed using the following equation: ? ? ? ? ? ? ? ? ? ? ? ? = 001.0 log10 2 input rms scale full scale full z v power gain error the difference between the measured and ideal full-scale input voltage range of the adc. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of clk+ and clkC and the time when all output data bits are within valid logic levels. noise (for any range within the adc) calculated as follows: ? ? ? ? ? ? ?? = 10 10001.0 dbfs dbc dbm noise signal snr fs zv where: z is the input impedance. fs is the full scale of the device for the frequency in question. snr is the value of the particular input level. signal is the signal level within the adc, reported in db below full scale. this value includes input levels both thermal and quantization noise.
ad9430 rev. e | page 24 of 44 power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise and distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. reported in dbc (degrades as signal level is lowered) or dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product ; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. reported in dbc (degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc. transient resp onse time the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. out-of-range recovery time the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
ad9430 rev. e | page 25 of 44 application notes theory of operation the ad9430 architecture is optimized for high speed and ease of use. the analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 12-bit core. for ease of use, the part includes an on-board reference and input logic that accepts ttl, cmos, or lvpecl levels. the digital output logic levels are user selectable as standard 3 v cmos or lvds (ansi-644 compatible) via pin s2. encode input any high speed adc is extremely sensitive to the quality of the sampling clock provided by the user. a track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the a/d output. for that reason, considerable care has been taken in the design of the clock inputs of the ad9430, and the user is advised to give careful thought to the clock source. the ad9430 has an internal clock duty cycle stabilization circuit that locks to the rising edge of clk+ and optimizes timing internally. this allows for a wide range of input duty cycles at the input without degrading performance. jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 30 mhz nominally. the loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamicall y, requiring a wait time of 1.5 s to 5 s after a dynamic clock frequency increase before valid data is available. this circuit is always on and cannot be disabled by the user. the clock inputs are internally biased to 1.5 v (nominal) and support either differential or single-ended signals. for best dynamic performance, a differential signal is recommended. an mc100lvel16 performs well in the circuit to drive the clock inputs, as illustrated in figure 50 . (for trace lengths >2 inches, a standard lvpecl termination is recommended rather than the simple pull-down as shown.) note that for this low voltage pecl device, the ac coupling is optional. pecl gate 510 510 0.1 f 0.1 f clk? ad9430 clk+ 02607-050 figure 50. driving clock inputs with lvel16 in interleaved mode, output data on port a is offset from output data changes on port b by one-half output clock cycle, as shown in figure 51 . interleaved mode parallel mode 02607-051 figure 51. table 9. output select coding s1 1 s2 1 s4 1 s5 1 (data format select) (lvds/cmos mode select) 2 (i/p select) (full-scale select) 3 mode 1 x x x twos complement 0 x x x offset binary x 0 1 x dual-mode cmos interleaved x 0 0 x dual-mode cmos parallel x 1 x x lvds mode x x x 1 full scale = 0.768 v x x x 0 full scale = 1.536 v 1 x = dont care. 2 s4 used in cmos mode only (s2 = 0). s1 to s5 all have 30 k resistive pull-downs on chip. 3 s5 full-scale adjust (see the section). analog input
ad9430 rev. e | page 26 of 44 analog input the analog input to the ad9430 is a differential buffer. for best dynamic performance, impedances at vin+ and vin C should match. the analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades significantly if the analog input is driven with a single- ended signal. a wideband transformer such as the mini-circuit? adt1-1wt can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip resistor divider to a nominal 2.8 v. (see the equivalent circuits section.) special care was taken in the design of the analog input section of the ad9430 to prevent damage and corruption of data when the input is overdriven. the nominal differential input range is approximately 1.5 v p-p ~ (768 mv 2). note that the best snr performance is achieved with s5 = 0 (full scale = 1.5). 2.8v 2.8v vin+ vin? 768mv s5 = gnd digitalout = all 1s digitalout = all 0s 02607-052 figure 52. differential analog input range 2.8v s5 = avdd 768mv vin+ vin? = 2.8v 2.8v 02607-053 figure 53. single-ended analog input range ds inputs (ds+, dsC) in cmos output mode, the data sync inputs (ds+, dsC) can be used in applications that require a given sample to appear at a specific output port (a or b) relative to a given external timing signal. the ds inputs can also be used to synchronize two or more adcs in a system to maintain phasing between port a and port b on separate adcs (in effect, synchronizing multiple dco outputs). when ds+ is held high (dsC low), the adc data outputs and clock do not switch and are held static. synchronization is accomplished by the assertion (falling edge) of ds+ within the timing constraints t sds and t hds , relative to a clock rising edge. (on initial synchronization, t hds is not relevant.) if ds+ falls within the required setup time (t sds ) before a given clock rising edge, n, the analog value at that point in time is digitized and available at port a, 14 cycles later in interleaved mode. the very next sample, n + 1, is sampled by the next rising clock edge and available at port b, 14 cycles after that clock edge. in dual-parallel mode, port a has a 15-cycle latency and port b has a 14-cycle latency, but data is available at the same time. driving the ds inputs of each adc by the same sync signal accomplishes this. an easy way to accomplish synchronization is by a one-time sync at power-on reset. note that when running the ad9430 in lvds mode, set ds+ to ground and dsC to 3.3 v, as the ds inputs are relevant only in cmos output mode, simplifying the design for some applications as well as affording superior snr/sinad performance at higher encode/analog frequencies. cmos outputs the off-chip drivers on the chip can be configured to provide cmos-compatible output levels via pin s2. the cmos digital outputs (s2 = 0) are ttl/cmos compatible for lower power consumption. the outputs are biased from a separate supply (drvdd), allowing easy interface to external logic. the outputs are cmos devices that swing from ground to drvdd (with no dc load). it is recommended to minimize the capacitive load the adc drives by keeping the output traces short (<1 inch, for a total c load < 5 pf). when operating in cmos mode, it is also recommended to place low value (20 ) series damping resistors on the data lines to reduce switching transient effects on performance.
ad9430 rev. e | page 27 of 44 a1 vref 1k sense 200 0.1 f disable a1 v dd k full scale + 1v 3.3v external 1.23v reference + + s5 = 0 ? > k = 1.24 s5 = 1 ? > k = 0.62 02607-054 lvds outputs the off-chip drivers on the chip can be configured to provide lvds-compatible output levels via pin s2. lvds outputs are available when s2 = vdd and a 3.74 k rset resistor is placed at pin 7 (lvdsbias) to ground. the rset resistor current is ratioed on-chip, setting the output current at each output equal to a nominal 3.5 ma (11 irset). a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. lvds mode facilitates interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor as close to the receiver as possible. it is recommended to keep the trace length three to four inches maximum and to keep differential output trace lengths as equal as possible. figure 54. using an external reference noise power ratio testing (npr) npr is a test that is commonly used to characterize the return path of cable systems where the signals are typically qam signals with a noise-like frequency spectrum. npr performance of the ad9430 was characterized in the lab yielding an effective npr = 56.9 db at an analog input of 19 mhz. this agrees with a theoretical maximum npr of 57.1 db for an 11-bit adc at 13.6 db backoff. the rms noise power of the signal inside the notch is compared with the rms noise level outside the notch using an fft. sufficiently long record lengths to guarantee a sufficient number of samples inside the notch are a requirement, as well as a high order band-stop filter that provides the required notch depth for testing. clock outputs (dco+, dcoC) the input encode is divided by two (in cmos mode) and available off chip at dco+ and dcoC. these clocks can facilitate latching off chip, providing a low skew clocking solution (see figure 2 ). the on-chip clock buffers should not drive more than 5 pf of capacitance to limit switching transient effects on performance. note that the output clocks are cmos levels when cmos mode is selected (s2 = 0) and are lvds levels when in lvds mode (s2 = v dd ), requiring a 100 differential termination at receiver in lvds mode. the output clock in lvds mode switches at the encode rate. voltage reference a stable and accurate 1.23 v voltage reference is built into the ad9430 (vref). the analog input full-scale range is linearly proportional to the voltage at vref. note that an external reference can be used by connecting the sense pin to vdd (disabling internal reference) and driving vref with the external reference source. no appreciable degradation in performance occurs when vref is adjusted 5%. a 0.1 f capacitor to ground is recommended at the vref pin in internal and external reference applications. float the sense pin for internal reference operation.
ad9430 rev. e | page 28 of 44 evaluation board, cmos mode the ad9430 evaluation board offers an easy way to test the ad9430 in cmos mode. it requires a clock source, an analog input signal, and a 3.3 v power supply. the clock source is buffered on the board to provide the clocks for the adc, latches, and data ready signals. the digital outputs and output clocks are available at two 40-pin connectors, p3 and p23. the pcb interfaces directly with adi standard dual-channel data capture board (hsc-adc-eval-dc) which, together with adi adc analyzer software, allows for quick adc evaluation. the board has several different modes of operation and is shipped in the following configurations: ? offset binary ? internal voltage reference ? cmos parallel timing ? full-scale adjust = low power connector power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). avdd, drvdd, and vdl are the minimum required power connections. table 10. power connector, cmos mode avdd 3.3 v analog supply for adc (350 ma) drvdd 3.3 v output supply for adc (28 ma) vdl 3.3 v supply for support logic and dac (350 ma) ext_vref optional external reference input vclk/v_xtal supply for clock buffer/optional crystal vamp supply for optional amp analog inputs the evaluation board accepts a 1.3 v p-p analog input signal centered at ground at smb connector j4. this signal is terminated to ground through 50 by r16. the input can be alternatively terminated at the transformer t1 secondary by r13 and r14. t1 is a wideband rf transformer providing the single-ended-to-differential conversion, allowing the adc to be driven differentially and minimizing even-order harmonics. an optional second transformer, t2, can be placed following t1 if desired. this provides some performance advantage (~1 db to 2 db) for high analog input frequencies (>100 mhz). if t2 is placed, two shorting traces at the pads need to be cut. the analog signal is low-pass filtered by r41, c12 and r42, and c13 at the adc input. gain full scale is set at e17, e18, and e19. connecting e17 to e18 sets s5 low, full scale = 1.5 v differential; connecting e17 to e19 sets s5 high, full scale = 0.75 v differential. encode the encode clock is terminated to ground through 50 at smb connector j5. the input is ac coupled to a high speed differential receiver (lvel16) that provides the required low jitter, fast edge rates needed for optimum performance. j5 input should be >0.5 v p-p. power to the el16 is set at jumper e47. connecting e47 to e45 powers the buffer from avdd; connecting e47 to e46 powers the buffer from vclk/v_xtal. voltage reference the ad9430 has an internal 1.23 v voltage reference. the adc uses the internal reference as the default when jumpers e24 to e27 and e25 to e26 are left open. the full scale can be increased by placing optional resistor r3. the required value varies with the process and needs to be tuned for the specific application. full scale can similarly be reduced by placing r4; tuning is required here as well. an external reference can be used by shorting the sense pin to 3.3 v (place jumper e26 to e25). the e27 to e24 jumper connects the adc vref pin to the ext_vref pin at the power connector. data format select data format select sets the output data format of the adc. setting dfs (e1 to e2) low sets the output format to be offset binary; setting dfs high (e1 to e3) sets the output to twos complement. i/p timing select output timing is set at e11, e12 and e13. e12 to e11 sets s4 low for parallel output timing mode. e11 to e13 sets s4 high for interleaved timing mode. timing controls flexibility in latch clocking and output timing is accomplished by allowing for clock inversion at the timing controls section of the pcb. each buffered clock is buffered by an xor and can be inverted by moving the appropriate jumper for that clock.
ad9430 rev. e | page 29 of 44 cmos data outputs the adc cmos digital outputs are latched on the board by four lvt574s; the latch outputs are available at the two 40-pin connectors at pin 11 through pin 33 on p23 (channel a) and pin 11 through pin 33 on p3 (channel b). the latch output clocks (data ready) are available at pin 37 on p23 (channel a) and pin 37 on p3 (channel b). the data-ready clocks can be inverted at the timing controls section if needed. ch1 ch2 ch2 m 5.00ns 1 2 ? : 4.6ns c1 freq 84.65608mhz 2.00v 2.00v 02607-055 figure 55. data output an d clock @ 80-pin connector crystal oscillator an optional crystal oscillator can be placed on the board to serve as a clock source for the pcb. power to the oscillator is through the vclk pin at the power connector (also called vclk/v_xtal). if an oscillator is used, ensure proper termination for best results. the board has been tested with a valpey fisher vf561 and a vectron jn00158-163.84. test results for the vf561 are shown in figure 56. mhz 0 ?30 080 20 db 40 60 ?60 ?80 ?20 ?10 ?50 ?40 ?100 ?90 ?70 encode 163.84mhz analog 65.02mhz snr 63.93db sinad 63.87db fund ?0.45dbfs 2nd ?85.62dbc 3rd ?91.31dbc 4th ?90.54dbc 5th ?90.56dbc 6th ?91.12dbc thd ?82.21dbc sfdr 83.93dbc samples 8k noiseflr ?100.44dbfs worstsp ?83.93dbc 02607-057 figure 56. fftusing vf561 crystal as clock source optional amplifier the evaluation board as shipped uses a wideband rf transformer in its analog path. a user can modify the board to use the ad8351 op amp for ac- or dc-coupled applications (see figure 59 and figure 60). figure 60 shows the ad8351 in an ac-coupled topology, while figure 57 shows the ad8351 in a dc-coupled application. optimum performance is obtained with the ad8351 ac coupled. single- ended 50 ? source r1 100nf 100nf ad8351 inhi inlo r g ophi oplo vocm digital out ad9430 ain+ ain? 100nf r f 5pf 2.8v 25 ? 25 ? 50 ? 25 ? 02607-078 figure 57. using the ad8351 on the ad9430 pcb
ad9430 rev. e | page 30 of 44 troubleshooting if the board does not seem to be working correctly, try the following: the ad9430 evaluation board is provided as a design example for customers of analog devices, inc. adi makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. ? verify power at ic pins. ? check that all jumpers are in the correct position for the desired mode of operation. ? verify that vref is at 1.23 v. ? run the clock and analog inputs at low speeds (10 msps/ 1 mhz) and monitor latch and adc for toggling. signal generator signal generator refin 10mhz refout band-pass filter analog j4 clock j5 ad9430 evaluation board avdd gnd drvdd gnd vdl gnd 3.3v 3.3v 3.3v + data capture and processing 02607-059 ? + ? + ? figure 58. evaluation board connections
ad9430 rev. e | page 31 of 44 table 11 . cmos pcb evaluation board bill of material no. quantity reference designator device package value comments 1 47 c1, c3Cc11, c15Cc44, c47, c48, c58Cc62 capacitor 0402 0.1 f c11, c18, c30, c33, c34, c39, c40, c48 not placed 2 1 c2 capacitor 0402 10 pf not placed 3 1 c12 capacitor 0402 20 pf not placed 4 29 c13, c14, c45, c46, c50Cc57, c68-c84 capacitor 0402 0.01 f all .01uf caps not placed 5 6 c49, c63Cc67 capacitor capl 10 f 6 8 (e3, e1, e2),( e19, e17, e18), (e13, e11, e12),( e46, e47, e45), (e35, e33, e34),( e32, e30, e31), (e29, e23, e28),( e22, e16, e21) 3-pin header/jumper 7 1 e26, e25, e27, e24 4-pin header/jumper 8 4 j1, j2, j4, j5 sma sma j2 not placed 9 2 p3, p23 1 connector 10 3 p4, p21, p22 4-pin power connector post z5.531.3425.0 wieland 11 3 p4, p21, p22 4-pin power connector detachable connector 25.602.5453.0 wieland 12 4 r1, r5, r16, r27 resistor 0402 50 r1 not placed 13 3 r2, r3, r4 resistor 0402 3.8k r3, r4 not placed 14 8 r6Cr8, r10, r33Cr36 resistor 0603 100 r34 not placed 15 2 r9, r11 resistor 0402 0 16 17 r12, r15, r21Cr26, r28Cr31, r37, r38, r43, r46, r47 resistor 0402 user selected all 17 not placed 17 6 r13, r14, r41, r42, r44, r45 resistor 0402 25 r13, r14, r44, r45 not placed 18 2 r17, r18 resistor 0402 510 19 2 r19, r20 resistor 0402 150 20 2 r39, r40 resistor 0402 1 k 21 8 rz1, rz2, rz3, rz4, rz5, rz6, rz7, rz8 resistor pack 220 so16res 742c163221jtr cts 22 1 l1 inductor 0603 user selected not placed 23 2 t1,t4 transformer cd542 mini-circuits adt1C1wt t4 not placed 24 2 t2,t3 optional macom transformer sm-22 etc1C1C13 not placed 25 1 u1 ad9430bsv (?210) tqfp100 adc 26 1 u2 mc100lvel16d so8nb clock buffer 27 1 u3 vcx86 so14nb xor 28 4 u4, u5, u6, u7 lvt574 so20 29 1 u8 jn00158 optional xtal not placed 30 1 u9 ad8351 amp 1 p3 and p23 are implemented as one physical 80-pin connector, the s amtec tsw-140-08-l-d-ra.
ad9430 rev. e | page 32 of 44 vcc vee dq dn qn vbb gnd e45 e46 vcc vclk e47 c36 0.1 f j5 gnd r27 50 c5 0.1 f encode 2 3 4 5 6 7 8 c8 0.1 f r18 510 r17 510 mc100l 10el16 u2 gnd r20 150 r19 150 gnd out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock u7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clklatb vdl gnd gnd r1 r2 r3 r4 r5 r6 r7 r8 rz5 220 rso16iso 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dy4 dy3 dy2 dy1 dy0 dya dyb r1 r2 r3 r4 r5 r6 r7 r8 rz4 220 rso16iso 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock u6 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clklata vdl gnd gnd r1 r2 r3 r4 r5 r6 r7 r8 rz6 220 rso16iso 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ory dy11 dy10 dy9 dy8 dy7 dy6 dy5 r1 r2 r3 r4 r5 r6 r7 r8 rz3 220 rso16iso 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c4oms p3 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 gnd drb gnd dy11 dy10 dy9 dy8 dy7 dy6 dy5 dy4 dy3 dy2 dy1 dy0 dya dyb ory gnd gnd out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock u4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 dm8 dm7 dm6 dm5 clklata vdl gnd gnd r1 r2 r3 r4 r5 r6 r7 r8 rz8 220 rso 16iso 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 orx dx11 dx10 dx9 dx8 dx7 dx6 dx5 r1 r2 r3 r4 r5 r6 r7 r8 rz1 220 rso16iso 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c4oms p23 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 gnd dra gnd dx11 dx10 dx9 dx8 dx7 dx6 dx5 dx4 dx3 dx2 dx1 dx0 dxa dxb orx gnd gnd out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock 74ac574m u5 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clklata vdl gnd gnd r1 r2 r3 r4 r5 r6 r7 r8 rz7 220 rso16iso 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dx4 dx3 dx2 dx1 dx0 dxa dxb r1 r2 r3 r4 r5 r6 r7 r8 rz2 220 rso16iso 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 p1 p2 p3 p4 1 2 3 4 gndamp vamp p4 ptmica04 p1 p2 p3 p4 1 2 3 4 gnd vdl vclk vref p21 ptmica04 p1 p2 p3 p4 1 2 3 4 gnd vcc gnd drvdd p22 ptmica04 e20 vdl e7 drvdd couta cout r9 0 coutab coutb r11 0 h4 mtholes h3 mtholes h2 mtholes h1 mtholes gnd u3 3 74a vc86 clklata r33 100 couta r10 100 e35 e34 vdl gnd e33 1 2 u3 6 74a vc86 dra r34 100 r8 100 e32 e31 vdl gnd e30 4 5 u3 8 74a vc86 clklatb r35 100 r7 100 e29 e28 vdl gnd e23 9 10 u3 11 74a vc86 drb r36 100 r6 100 e22 e21 vdl gnd e16 12 13 p16 gnd ground pad under part 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 u1 ad9430 dr vdd gnd gnd cout coutb drvdd gnd drvdd gnd drvdd gnd gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc vcc vcc gnd gnd gnd dr vdd gnd gnd vcc gnd vcc gnd vcc vcc vcc gnd gnd c4 0.1 f vcc gnd e14 gnd r5 50 j1 gnd r1 50 j2 notes 1. to use single ended analog input, remove c6, c43, and c47 place c33, c34, r44 and r45 e1 e3 vcc e2 gnd ?enc gnd vcc gnd gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc e11 e13 vcc e12 gnd e8 e10 vcc e9 gnd r40 1k gnd e4 e6 vcc e5 gnd r39 1k gnd c13 0.01 f gnd e27 e26 vcc e24 vref e25 r4 3.8k r3 3.8k gnd gnd e17 e19 vcc e18 gnd c10 0.1 f c9 0.1 f couta coutab coutab 02607-060 74ac574m 74ac574m 74ac574m gnd gnd el outb el out gnd r2 3.8k c1 0.1 f gnd c2 10pf gnd j4 gnd gnd r16 50 analog optin c6 0.1 f c7 0.1 f gnd e15 inx t1 6 4 5 1 3 2 gnd 6 4 5 1 3 2 t4 r44 25 c34 0.1 f c12 20pf r42 25 r41 25 ampin ampinb c3 0.1 f c43 0.1 f c47 0.1 f r14 25 r13 25 opin opinb c33 0.1 f r45 25 see note 1 for single ended input q see note 1 for single ended input figure 59. evaluation board schematiccmos
ad9430 rev. e | page 33 of 44 02607-077 c68 0.01 f vcc gnd place r30 or r31 (power down) e/d 1 nc 2 gnd 3 vcc outputb output 6 5 4 jn00158 u8 gnd r15 100 r38 100 gnd vclk vclk gnd r21 100 r22 100 vclk gnd r23 100 r24 100 p1 p2 + c64 10 f c16 0.1 f c17 0.1 f c19 0.1 f c21 0.1 f c20 0.1 f c23 0.1 f c22 0.1 f c25 0.1 f c24 0.1 f c27 0.1 f c26 0.1 f c29 0.1 f c28 0.1 f c31 0.1 f c32 0.1 f c35 0.1 f vcc gnd c38 0.1 f c69 0.01 f c70 0.01 f c71 0.01 f c72 0.01 f c73 0.01 f c74 0.01 f c75 0.01 f c76 0.01 f c77 0.01 f c78 0.01 f c79 0.01 f c80 0.01 f c81 0.01 f c82 0.01 f c83 0.01 f c84 0.01 f c67 10 f vdl gnd c46 0.01 f c50 0.01 f c51 0.01 f c52 0.01 f c45 0.01 f c44 0.1 f c42 0.1 f c41 0.1 f c15 0.1 f c37 0.1 f c65 10 f drvdd gnd c62 0.1 f c60 0.1 f c59 0.1 f c58 0.1 f c53 0.01 f c54 0.01 f c55 0.01 f c56 0.01 f c57 0.01 f c66 10 f c14 0.01 f vclk gnd + c63 10 f vref gnd + c49 10 f c48 0.1 f vamp gnd + vocm vpos ophi oplo comm pwdn rgp1 inhi inlo rgp2 gnd gnd rgp1 vamp gnd rgp1 r12 25 r25 1.2k r31 1k r30 1k r43 25 c11 0.1 f r29 0 gnd optin r37 25 vamp ampinb ampin c39 0.1 f c40 0.1 f r47 25 r46 25 gnd gnd gnd inx opin opinb t3 etc1-1-13 t2 etc1-1-13 15 15 2 2 34 34 pr sec pr sec gnd vamp to use vf561c crystal l1 x l is optional c18 0.1 f c30 0.1 f 1 2 3 4 5 10 9 8 7 6 r26 1k r28 1k + + c61 0.1 f ad8351 u9 figure 60. evaluation board schematiccmos (continued)
ad9430 rev. e | page 34 of 44 02607-081 figure 61. pcb top- side silkscreen 02607-082 figure 62. pcb top-side copper 02607-083 figure 63. pcb ground layer 02607-084 figure 64. pcb split power plane
ad9430 rev. e | page 35 of 44 02607-085 figure 65. pcb bottom-side copper 02607-086 figure 66. pcb bottom-side silkscreen
ad9430 rev. e | page 36 of 44 evaluation board, lvds mode the ad9430 evaluation board offers an easy way to test the ad9430 in lvds mode. (the board is also compatible with the ad9411.) it requires a clock source, an analog input signal, and a 3.3 v power supply. the clock source is buffered on the board to provide the clocks for the adc, latches, and a data-ready signal. the digital outputs and output clocks are available at a 40-pin connector, p23. the board has several different modes of operation and is shipped in the following configurations: ? offset binary ? internal voltage reference ? full-scale adjust = low note that the ad9430 lvds evaluation board does not interface directly with the standard analog devices dual- channel data capture board (hsc-adc-eval-dc). an lvds- to-cmos translation board is required and is available from analog devices. (no translation board is required for the ad9430 cmos evaluation board.) power connector power is supplied to the board via a detachable 8-lead power strip (two 4-pin blocks). in tabl e 12 , vcc, drvdd, and vdl are the minimum required power connections, and the lvel16 clock buffer can be powered from vcc or vdl at the e47 jumper. table 12. power connector, lvds mode vcc 3.3 v analog supply for adc (350 ma) drvdd 3.3 v output supply for adc (50 ma) vdl 3.3 v supply for support logic ext_vref optional external reference input analog inputs the evaluation board accepts a 1.3 v p-p analog input signal centered at ground at smb connector j4. this signal is terminated to ground through 50 by r16. the input can be alternatively terminated at the t1 transformer secondary by r13 and r14. t1 is a wideband rf transformer providing the single- ended-to-differential conversion, allowing the adc to be driven differentially and minimizing even-order harmonics. an o ptional second transformer, t2, can be placed following t1 if desired. this provides some performance advantage (~1 to 2 db) for high analog input frequencies (>100 mhz). if t2 is placed, two shorting traces at the pads need to be cut. the analog signal can be low-pass filtered by r41, c12 and r42, and c13 at the adc input. a wideband differential amplifier (ad8351) can be configured on the pcb for dc-coupled applications. remove c6, c15, and c30 to prevent transformer loading of the amp. see figure 67 , figure 68 , and figure 69 for more information. gain full scale is set at e17 to e19, e17 to e18 sets s5 low, full scale = 1.5 v differential; e17 to e19 sets s5 high, full scale = 0.75 v differential. best performance is obtained at 1.5 v full scale. clock the clock input is terminated to ground through a 50 resistor at smb connector j5. the input is ac coupled to a high speed differential receiver (lvel16) that provides the required low jitter, fast edge rates needed for optimum performance. j5 input should be >0.5 v p-p. power to the lvel16 is set at jumper e47. e47 to e45 powers the buffer from avdd; e47 to e46 powers the buffer from vclk/v_xtal (not in table 11). voltage reference the ad9430 has an internal 1.23 v voltage reference. the adc uses the internal reference as the default when jumpers e24 to e27 and e25 to e26 are left open. the full scale can be increased by placing optional resistor r3. the required value varies with the process and needs to be tuned for the specific application. full scale can similarly be reduced by placing r4; tuning is required here as well. an external reference can be used by shorting the sense pin to 3.3 v (place jumper e26 to e25). jumper e27 to e24 connects the adc vref pin to the ext_vref pin at the power connector. data format select data format select (dfs) sets the output data format of the adc. setting dfs low (e1 to e2) sets the output format to be offset binary; setting dfs high (e1 to e3) sets the output to twos complement. data outputs the adc lvds digital outputs are routed directly to the connector at the card edge. resistor pads have been placed at the output connector to allow for termination if the connector receiving logic does not have the required differential termination for the data bits and dco. each output trace pair should be terminated differentially at the far end of the line with a single 100 resistor. crystal oscillator an optional crystal oscillator can be placed on the board to serve as a clock source for the pcb. power to the oscillator is through the vdl pin at the power connector. if an oscillator is used, ensure proper termination for best results. the board has been tested with a valpey fisher vf561 and a vectron jn00158- 163.84.
ad9430 rev. e | page 37 of 44 table 13. lvds pcb evaluation board bill of material no. quantity reference designator device package value comment 1 33 c1, c4Cc11, c15Cc17, c19Cc32, c35, c36, c58Cc62 c3, c18, c39, c40 capacitors 0603 0.1 f c3, c18, c39, c40 not placed 2 4 c33, c34, c37, c38 capacitor 0402 0.1 f c33, c34, c37, c38 not placed 3 4 c63Cc66 capacitor tajd capl 10 uf 4 1 c2 capacitor 0603 10 pf c2 not placed 5 2 c12, c13 capacitor 0603 20 pf c12, c13 not placed 6 2 j4, j5 jacks smb 7 2 p21, p22 power connectors top 25.602.5453.0 wieland 8 2 p21, p22 power connectors posts z5.531.3425.0 wieland 9 1 p23 40-pin right-angle connector digi-key s2131-20-nd 10 16 r1, r6Cr12, r15, r31Cr37 resistor 0402 100 r1, r6Cr12, r15, r31C37 not placed 11 1 r2 resistor 0603 3.8 k 12 3 r5, r16, r27 resistor 0603 50 13 2 r17, r18 resistor 0603 510 14 2 r19, r20 resistor 0603 150 15 2 r29, r30 resistor 0603 1 k 16 2 r41, r42 resistor 0603 25 17 2 r3, r4 resistor 0603 3.8 k 18 2 r13, r14 resistor 0603 25 r13, r14 not placed 19 6 r22, r23, r24, r25, r26, r28 resistor 0603 100 r22, r23, r24, r25, r26, r28 not placed 20 4 r39, r40, r45, r47 resistor 0402 25 r39, r40, r45, r47 not placed 21 2 r43, r44 resistor 0402 10 k r43, r44 not placed 22 1 r46 resistor 0402 1.2 k r46 not placed 23 3 r38, r48, r49 resistor 0402 25 r38, r48, r49 not placed 24 2 r50, r51 resistor 0402 1 k r50, r51 not placed 25 1 t1 t2 rf transformer mini-circuits adt1-1wt t2 not placed 26 1 u2 rf amp ad8351 27 1 u9 optional crystal oscillator jn00158 or vf561 28 1 u1 ad9430 tqfp-100 29 1 u3 mc100lvel16 so8nb
ad9430 rev. e | page 38 of 44 gnd 40 drb 38 gnd 36 d11b 34 d10b 32 gnd dr gnd d11 d10 39 37 35 33 31 d9b 30 d8b 28 d7b 26 d6b 24 d5b 22 d9 d8 d7 d6 d5 29 27 25 23 21 d4b 20 d3b 18 d2b 16 d1b 14 d0b 12 d4 d3 d2 d1 d0 19 17 15 13 11 d1fb 10 d2fb 8 dorb 6 4 gnd 2 d1f d2f do r gnd 9 7 5 3 1 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 r1 100 dor dorb r6 100 d11 d11b r7 100 d10 d10b r8 100 d9 d9b r15 100 d1 d1b r36 100 d0 d0b r35 100 d1f d1fb r34 100 d2f d2fb r31 100 d2 d2b r10 100 d6 d6b r37 100 dr drb r32 100 d3 d3b r11 100 d7 d7b r9 100 d5 d5b r33 100 d4 d4b r12 100 d8 d8b gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc vcc vcc gnd gnd drvdd gnd drvdd drvdd drvdd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc gnd gnd gnd gnd gnd drvdd gnd ~enc vcc c4 0.1 f gnd gnd r5 50 c10 0.1 f c9 0.1 f elout eloutb gnd r19 150 r20 150 gnd c36 0.1 f vcc vee vbb dn d q qn 2 3 4 5 6 7 8 gnd r18 510 r17 510 c8 0.1 f vcc e46 e47 vdl e45 10el16 u3 j5 gnd gnd c5 0.1 f encode r27 50 c13 20pf gnd gnd vcc gnd gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc c12 20pf c15 0.1 f c3 0.1 f c2 10pf c30 0.1 f c7 0.1 f c11 0.1 f c6 0.1 f j4 gnd r16 50 r14 25 r42 25 t2 optional gnd gnd r13 25 gnd ampinb ampin r41 25 t1 adt1-1wt 1 5 3 4 2 6 t2 adt1-1wt 1 5 3 4 2 6 nc nc pri sec pri sec gnd gnd amp analog vcc e19 vcc e3 e17 gnd gnd e18 r30 1k vcc r29 1k e1 gnd e2 r2 3.8k gnd gnd r3 3.8k r4 3.8k vcc e26 vref e24 e25 e27 gnd c1 0.1 f p16 gnd ground pad under part p1 p2 1 2 gnd vref p3 p4 3 4 gnd vdl p1 p2 1 2 gnd drvdd p3 p4 3 4 gnd vcc p21 ptm1cro4 p22 ptm1cro4 h4 mthole6 h3 mthole6 h2 mthole6 h1 mthole6 gnd connector 02607-068 figure 67. evaluation board schematiclvds
ad9430 rev. e | page 39 of 44 02607-069 + c64 10 f c16 0.1 f c17 0.1 f c19 0.1 f c21 0.1 f c20 0.1 f c23 0.1 f c22 0.1 f c25 0.1 f c24 0.1 f c27 0.1 f c26 0.1 f c29 0.1 f c28 0.1 f c31 0.1 f c32 0.1 f c35 0.1 f vcc gnd + c65 10 f c61 0.1 f c62 0.1 f c60 0.1 f c59 0.1 f c58 0.1 f drvdd gnd c66 10 f c18 0.1 f vdl gnd + c63 10 f vref gnd + to use vf561 crystal e/d 1 nc 2 gnd 3 vcc outputb output 6 5 4 jn00158 u9 gnd r28 100 r22 100 gnd vdl vdl gnd r23 100 r25 100 vdl gnd r24 100 r26 100 p4 p5 figure 68. evaluation board schematiclvds (continued) vdl vdl gnd gnd gnd amp in amp power down use r43 or r44 u2 ad8351 r44 r39 25 r38 r40 25 r46 r45 25 r43 c33 0.1 f c34 0.1 f vdl gnd gnd r51 1k r50 1k c38 0.1 f c37 0.1 f r49 c39 0.1 f r48 c40 0.1 f ampinb ampin gnd r47 pwup 1 rgp1 2 inhi 3 inlo 4 rpg2 5 vocm vpos ophi oplo comm 10 9 8 7 6 25 25 25 1.2k 0 10k 10k 02607-079 figure 69. evaluation board schematiclvds (continued)
ad9430 rev. e | page 40 of 44 f 02607-071 figure 70. pcb top-si de silkscreenlvds 02607-072 figure 71. pcb top-side copperlvds 02607-073 figure 72. pcb ground layerlvds 02607-074 figure 73. pcb split power planelvds
ad9430 rev. e | page 41 of 44 02607-075 figure 74. pcb bottom-side copperlvds 02607-076 figure 75. pcb bottom-side silkscreenlvds
ad9430 rev. e | page 42 of 44 outline dimensions compliant to jedec standards ms-026-aed-hd 021809-a 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.27 0.22 0.17 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max 1 25 26 50 76 100 75 51 6.50 nom 7 3.5 0 coplanarity 0.08 0.20 0.09 top view (pins down) bottom view (pins up) conductive heat sink pin 1 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 76.100-lead thin quad fl at package, exposed pad [tqfp_ep] (sv-100-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9430BSV-170 ?40c to +85c 100-lead thin quad flat package, exposed pad (tqfp_ep) sv-100-1 ad9430bsvz-170 ?40c to +85c 100-lead thin quad flat package, exposed pad (tqfp_ep) sv-100-1 ad9430bsv-210 ?40c to +85c 100-lead thin quad flat package, exposed pad (tqfp_ep) sv-100-1 ad9430bsvz-210 ?40c to +85c 100-lead thin quad flat package, exposed pad (tqfp_ep) sv-100-1 1 z = rohs compliant part.
ad9430 rev. e | page 43 of 44 notes
ad9430 rev. e | page 44 of 44 notes ?2005C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02607-0-9/10(e)

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